· BS/MS Electrical Engineering/ Computer Engineering or equivalent
· 5+ years industry experience in the field of RTL design and/or RTL functional verification
· Knowledge of Verilog or VHDL hardware description languages
· Knowledge of design and verification life cycle and tools (primarily simulation)
· Knowledge of advance verification methodologies such as constrained-random simulation, functional coverage and verification best practices is preferred
· Knowledge of Assertion Based Verification or formal model checking is preferred
· Good command of the English language, courteous manners, and ability to promote Atrenta products and corporate image through confidence, attention to detail, and reliability. Skill in English is a strong plus.
· Some overnight travel will be required